Renesas Electronics /R7FA6E2BB /CANFD_B /CFDRFCC0

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Interpret as CFDRFCC0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RFE 0 (0)RFIE 0 (000)RFPLS0 (000)RFDC0 (0)RFIM 0 (000)RFIGCV

RFIM=0, RFDC=000, RFIE=0, RFE=0, RFPLS=000, RFIGCV=000

Description

RX FIFO Configuration/Control Registers 0

Fields

RFE

RX FIFO Enable

0 (0): FIFO disabled

1 (1): FIFO enabled

RFIE

RX FIFO Interrupt Enable

0 (0): FIFO interrupt generation disabled

1 (1): FIFO interrupt generation enabled

RFPLS

Rx FIFO Payload Data Size Configuration

0 (000): 8 bytes

1 (001): 12 bytes

2 (010): 16 bytes

3 (011): 20 bytes

4 (100): 24 bytes

5 (101): 32 bytes

6 (110): 48 bytes

7 (111): 64 bytes

RFDC

RX FIFO Depth Configuration

0 (000): FIFO Depth = 0 message

1 (001): FIFO Depth = 4 messages

2 (010): FIFO Depth = 8 messages

3 (011): FIFO Depth = 16 messages

4 (100): FIFO Depth = 32 essages

5 (101): FIFO Depth = 48 messages

6 (110): Reserved

7 (111): Reserved

RFIM

RX FIFO Interrupt Mode

0 (0): Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV

1 (1): Interrupt generated at the end of every received message storage

RFIGCV

RX FIFO Interrupt Generation Counter Value

0 (000): Interrupt generated when FIFO is 1/8th full

1 (001): Interrupt generated when FIFO is 1/4th full

2 (010): Interrupt generated when FIFO is 3/8th full

3 (011): Interrupt generated when FIFO is 1/2 full

4 (100): Interrupt generated when FIFO is 5/8th full

5 (101): Interrupt generated when FIFO is 3/4th full

6 (110): Interrupt generated when FIFO is 7/8th full

7 (111): Interrupt generated when FIFO is full

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